As device input and output performance (e.g., speed) requirements increase, technology changes to meet these requirements. Increased transistor performance is typically achieved by reducing the gate-oxide thickness and shortening the channel length via lithographic size reduction. One of the disadvantages of a thinner gate-oxide layer is reduced transistor voltage tolerance. In general, the greater the performance that a transistor is designed to achieve, the lower the voltage that the transistor can tolerate. Effects such as hot-carrier injection and gate-oxide breakdown are the cause of signal and supply limitations on faster devices.
One possible approach to handling over-voltage conditions would be to implement I/O circuits with slower transistors having higher voltage tolerance. Unfortunately, this reduces the bandwidth of signal interfaces that the I/O circuits can successfully accommodate.
Another approach is to use programmable protection. Since this type of protection is changeable by programming, it is limited to a specific mode of operation before the device is configured. Unfortunately, this type of power supply selection and protection can lead to non-optimal performance, power, and signal disturbance issues before the device is configured, since the device I/O circuits can be optimized for only a minimal set of conditions. When those conditions are not met, the I/O circuits may cause surges in pad current and power supply current or actual part failure.
I/O circuits are preferably versatile enough to meet all of the performance requirements of numerous interface standards, including hot-plug and power-sequencing requirements, and be voltage tolerant before the device is programmed. Prior-art circuits use numerous power supplies and different circuit sections for different signaling applications. This leads to inefficiencies when one or more of the different signaling applications, and therefore one or more of the corresponding different circuit sections, are not utilized.